One of the main concerns of computer design is obtaining the highest possible operating speed. An adder plays a central role in the operation of computers as well as numerous other systems, and is thus a major factor in determining the overall speed of many systems.
A number of fast adders have been developed. The simplest form of parallel adder is the ripple-carry adder which accepts the two numbers to be summed and a carry-in as inputs and creates a sum and a carry-out bit. In this case, each bit of the addend and augend is fed into a full adder along with the carry out of the next highest significant bit. In the worst possible case, the carry may have to propagate, ie. "ripple-through", the adder from one end to another, thus causing a long delay. If a large number of bits must be added, such as 64 or 128, this delay may be intolerable.
Another type of adder is the minimum delay adder which takes advantage of the basic theorem that any Boolean function, no matter how complex, may be realized in a second-order form. In this case, there is no ripple-through delay. The number of logic gates required, however, is far too large to make a practical adder. For example, a 64-bit adder would require over 10.sup.20 gates--obviously an impractical situation.
The carry look-ahead adder combines the concepts of the carry-propagate and minimum delay adders to reach compromise between the delay time and the number of gates. Although better than the two previous examples, the carry look-ahead adder is still not sufficient for many high speed, multi-bit applications.
The conditional sum adder is a well known adder which is faster than the previously mentioned adders. In this case, the sum and carry-out of each bit are computed twice for both carry-in equal to zero and carry-in equal to one. Groups of two sums and carry-outs are then formed. Within each group, the carry-out of the least significant half is used to select the new sum and carry-out of the most significant half. This operation of grouping of 4-bit, 8-bit, 16-bit, etc. is repeated until the group size matches the adder word length.
Although in theory, the conditional sum adder is the fastest adder, the speed is often limited by the high fanout nets in the critical path (the carry-out of the least significant half in a group has to select all the sums and carry-outs of the most significant half). In prior art applications, people have tried to build conditional sum adders with multiple cascaded CMOS buffers in order to drive the high fanout nets. The additional buffers introduce more delay into the critical path. Also, the word length dependent customized buffers also break the basically regular structure of the conditional sum adder and thus complicate the layout and fabrication of the device.
Accordingly, improvements which overcome any or all of the problems are presently desirable.